1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device in which programming and erasing are possible electrically. More particularly, the present invention relates to a non-volatile semiconductor memory device in which a memory cell has a floating gate structure, and a semiconductor device including the non-volatile semiconductor memory device.
2. Description of the Related Art
Conventionally, in a non-volatile semiconductor memory device such as a flash memory and the like, a floating gate made of poly-silicon and the like is formed on a gate oxide film of an n-type MOS transistor. An insulating film such as an ONO (Oxide-Nitride-Oxide) film and the like is formed on the floating gate. A control gate is formed on the insulating film. Each memory cell has such a structure, and a plurality of memory cells are arranged in matrix form. According to the non-volatile semiconductor memory device having such a configuration, the floating gate as a charge accumulation layer is electrically insulated from the other portions, and data is stored by injecting electrons into the floating gate of a memory cell.
High performance, low voltage, and low power are major issues for a flash memory. A technology for achieving a flash memory with fast access times is described, for example, in T. Ogura et al., “Embedded Twin MONOS Flash Memories with 4 ns and 15 ns Fast Access Times”, 2003 Symposium on VLSI Circuits Digest of Technical Papers.
Recently, in order to reduce the operation voltage and the power consumption of a transistor, it is considered to form a gate insulating film by using high dielectric constant materials. Such a high dielectric constant film (a high-k film) is described, for example, in H. Iwai, “Subject toward practical application of high-k gate insulating film”, 57-th VLSI FORUM, VLSI Report, Feb. 23, 2001, pp. 13–28. For the same reason, it is also proposed in the field of the non-volatile semiconductor memory device to form a charge accumulation layer by using high dielectric constant materials such as strontium titanate, BST (barium strontium titanate) and so on, as disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-326681) which will be referred to as a patent document.
FIG. 1 is a cross-sectional view showing a memory cell of a non-volatile semiconductor memory device disclosed in the patent document. As shown in FIG. 1, a memory cell 100 of the non-volatile semiconductor memory device is configured as follows. A source 105 and a drain 106 are formed in a silicon substrate 101. A channel region is formed between the source 105 and the drain 106. A first insulating film 102 is formed on the channel region, which is a silicon oxide film having a thickness of 2.5 to 5.0 nm. A second insulating film 103 which serves as the charge accumulation layer is formed on the first insulating film 102. The second insulating film 103 has a thickness of 50 to 100 nm, and is made of strontium titanate, barium strontium titanate, and barium titanate and the like. The second insulating film 103 is a high dielectric constant film. A control gate 104 made of doped poly-silicon (for example, phosphor doped poly-silicon) is formed on the high dielectric constant film 103.
Also, a non-volatile semiconductor memory device is proposed in the patent document, in which a silicon grain (hereinafter, referred to as a Si grain) whose grain diameter is not larger than 10 Å is used as a floating gate. FIG. 2 is a cross-sectional view showing a memory cell of the non-volatile semiconductor memory device which uses Si grains. As shown in FIG. 2, a memory cell 110 of the non-volatile semiconductor memory device is configured as follows. A source 105 and a drain 106 are formed in a silicon substrate 101. A channel region is formed between the source 105 and the drain 106. A first insulating film 102 is formed on the channel region, which is a silicon oxide film having a thickness of 2.5 to 3.0 nm. A large number of Si grains 107 are formed on the first insulating film 102 as a floating gate. Each Si grain 107 is made of micro powder of silicon crystal or silicon cluster whose grain diameter is equal to or less than 1 nm. A second insulating film 103 is formed to cover the first insulating film 102 and the Si grains 107. The second insulating film 103 has a thickness of about 50 nm, and is made of strontium titanate, barium strontium titanate, and barium titanate and the like. A control gate 104 made of doped poly-silicon is formed on the second insulating film 103.
When programming of the memory cell is performed, for example, the source 105 and the substrate 101 are grounded, and a high voltage is applied to the control gate 104 and the drain 106. Accordingly, electrons move in the channel region at a high speed from the source 105 to the drain 106. Then, the electrons acquiring a high energy in the vicinity of the drain 106 pass through the silicon oxide film 102 and are injected into the Si grains 107 which is the floating gate. As a result, the floating gate is negatively charged, and hence a threshold voltage observed from the control gate 104 becomes high.
On the other hand, when erasing of the memory cell is performed, the source 105 is opened, and the control gate 104 and the substrate 101 are grounded. Then, when a high voltage is applied to the drain 106, the electrons stored in the Si grains 107 are pulled out to the drain 106, and thus the potential of the floating gate is returned to neutral. As a result, the threshold voltage observed from the control gate 104 is returned to the state prior to the programming.
According to the non-volatile semiconductor memory device having the cell structure as shown in FIG. 2, the charge accumulation layer is made of the high dielectric constant material, which increases a capacity between the Si grains 107 and the control gate 104. It is therefore possible not only to reduce the voltages at the times of the programming and erasing but also to greatly reduce the programming and erasing times.
However, the conventional techniques mentioned above have the following problems. In the non-volatile semiconductor memory device described in the above-mentioned patent document, such materials as tantalum pentoxide, strontium titanate, barium strontium titanate, lead-zirconate-titanate and the like are used for forming the second insulating film 103. When thermally treated at a high temperature, these materials react with silicon components included in the control gate 104 and the Si grains 107. Therefore, it is not possible to perform the thermal treatment at a high temperature after the formation of the second insulating film 103. For example, when the material of the second insulating film 103 reacts with the silicon in the control gate 104, not only a silicon oxide film is formed but also metal is generated, which causes the variation in properties and the leak current. Also, when the material of the high dielectric constant film 103 and the silicon in the Si grain 107 react with each other, a silicon oxide film (an SiO2 film) is formed on the surface of the Si grain 107. In this case, a region for accumulating the charge is reduced. Also, the metal generated by the reaction causes the deterioration in the charge holding property. Therefore, it is necessary to carry out at a low temperature the thermal treatment which should be performed after the formation of the second insulating film 103 such as a thermal treatment for activating the source and drain and the like. In other words, the manufacturing processes are limited according to the non-volatile semiconductor memory device disclosed in the above-mentioned patent document.
As for the control gate 104, it is possible to prevent the control gate 104 from reacting with the silicon by forming a barrier film such as a silicon nitride film and the like between the control gate 104 and the high dielectric constant film 103. However, to provide the barrier film is not preferable in that the barrier film causes increase in the driving voltage.